1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, selected embodiments of the invention relate to flash memory devices and related methods for performing multi-block erase operations.
2. Description of Related Art
A flash memory device comprises a plurality of memory cells arranged in a matrix. Typically, the memory cells are programmed or read individually or in page units and are erased in units of memory blocks or sectors.
In a conventional erase operation of a NOR flash memory device, a voltage of about 6 to 10V is applied to a bulk region of a selected memory block region and a voltage about −10V is applied to corresponding selected word lines while corresponding selected bit and source lines are maintained in a floating state. Under these bias conditions, stored electrons are removed from the floating gates of selected memory cells via Fowler-Nordheim (FN) tunneling.
In more recent flash memory devices, this conventional erase operation is simultaneously used on multiple memory blocks in a multi-block erase operation. Typically, the multi-block erase operation simultaneously erases at least one block from each of a plurality of memory banks. By using the multi-block erase operation, the time required to simultaneously erase several blocks can be significantly reduced. Such a reduction in erase time can be especially useful, for example, during test operations where large numbers of memory blocks are erased.
FIG. 1 is a waveform diagram of bulk voltages applied to selected memory banks during a conventional multi-block erase operation of a NOR-type flash memory device. Referring to FIG. 1, during a first erase period ERS_1, bulk voltages applied to selected memory blocks in corresponding banks BANK<0> through BANK<N−1> are increased or “stepped up” in successive erase loops. Then, during and a second erase period ERS_2, the bulk voltages applied to the selected memory blocks are maintained at a substantially constant voltage level for several erase loops.
In each erase loop of first erase period ERS_1, an erase operation is performed and then an erase-verify operation is performed to detect whether all selected memory cells in each selected memory block have been successfully erased. In second erase period ERS_2, the bulk voltages of the selected memory blocks are maintained at the predetermined voltage level in order to establish a desired threshold voltage distribution in the selected memory cells of each selected memory block.
In the diagram of FIG. 1, a dotted line illustrates a bulk voltage level at which each selected memory block in each corresponding bank is detected to be successfully erased. For example, the selected memory block in bank BANK<0> is detected to be successfully erased in a fifth erase loop of first erase period ERS_1, the selected memory block in bank BANK<1> is detected to be successfully erased in a fourth erase loop of first erase period ERS_1, and the selected memory block in bank BANK<N−1> is detected to be successfully erased in a third erase loop of first erase period ERS_1.
As illustrated by FIG. 1, the same bulk voltages are applied to all of the selected memory blocks throughout the multi-block erase operation, regardless of when each block is detected to be successfully erased.